1. Field of the Invention
The invention relates to data communications apparatus and more particularly to a circuit and a method for extracting a clock signal from a serial data stream.
2. Description of the Relevant Art
Data communication between digital systems is typically achieved by converting parallel data to serial data at a transmitting port, sending the serial data in a stream through a transmission medium to a receiving port, and reconverting the serial data stream to parallel data at the receiving port. The parallel-to-serial conversion is required since many common carriers, such as modems and telephone lines, are limited to serial transmission.
A major consideration involved with the data communication is synchronization of the serial-to-parallel conversion at the receiving port. The serial data stream must be sampled at the proper time and rate to assure accurate serial-to-parallel conversion.
An internal clock of the receiving port typically controls the sampling of the serial data stream, and hence, the phase and frequency of this internal clock must be synchronized with the incoming data stream. Many systems have been designed wherein a phase-locked loop circuit is utilized to lock the internal clock signal to the serial data stream. Other systems have been proposed wherein control bits are inserted within the serial data stream at the transmitting port. The control bits consequently provide "time markers" to trigger the internal clock. In either case, such prior art systems are often limited to low transmission frequencies or are associated with a high cost.